Recently, with lower powering of systems and miniaturization of semiconductor processes, supply voltages (hereinafter, referred to as external power supply voltages) of chips have gone to lower voltage levels. However, it is difficult for all chips to go to a lower voltage at the same time. Thus, reducing the power of overall systems often lags behind that of single chips, and there coexist systems that may supply different external power supply voltages. Accordingly, chips may be equipped with a voltage converting device that generates a constant internal power supply voltage regardless of different external power supply voltages. As this voltage converting device may be located in a chip, it may be possible to apply the same chip to systems that supply different external power supply voltages.
FIG. 1 is a block diagram showing a conventional internal power supply voltage generating device.
Referring to FIG. 1, a conventional internal power supply voltage may have a reference voltage generating part 10 for generating a reference voltage VREF using an external power supply voltage VDD_EXT, and an internal power supply voltage generating part 11.
The reference voltage generating part 10 and the internal power supply voltage generating part 11 may be supplied with an external voltage, for example, an external power supply voltage VDD_EXT, as an operating voltage. The reference voltage generating part 10 may be a band-gap reference (BGR) circuit that is well known in the art, for example.
When the external power supply voltage VDD_EXT is supplied to a chip, the reference voltage generating part 10 may generate a reference voltage VREF, and the internal power supply voltage generating part 11 may convert the external power supply voltage VDD_EXT into an internal power supply voltage VDD_INT based on the reference voltage VREF. The internal power supply voltage VDD_INT may be generated as described below.
The internal power supply voltage generating part 11 may receive the external power supply voltage VDD_EXT, and generate the internal power supply voltage VDD_INT of a given level based on the reference voltage VREF generated in an integrated circuit device. Because the internal power supply voltage generating part 11 may generate the internal power supply voltage VDD_INT using the reference voltage VREF, the reference voltage generating part 10 may use the external power supply voltage VDD_EXT as its operating voltage.
The external power supply voltage VDD_EXT may be different based on which systems the semiconductor integrated circuit devices are applied. While the external power supply voltage VDD_EXT may be varied within a wide voltage range, the reference voltage, which is essentially constant regardless of variation in the external power supply voltage, enables a constant internal power supply voltage VDD_INT to be obtained. But, the following problem may arise from a semiconductor integrated circuit device adopting an internal power supply voltage generating device illustrated in FIG. 1.
When an internal power supply voltage generating device illustrated in FIG. 1 is applied to a system, an internal power supply voltage VDD_INT and a reference voltage VREF may need to be maintained at a constant level regardless of a voltage (for example, an external power supply voltage) supplied from the system. In order to maintain the internal power supply voltage VDD_INT, the reference voltage VREF may have to be maintained constant regardless of variation of the external power supply voltage VDD_EXT, or at least within a voltage range where the external power supply voltage may be varied.
For example, consider a system where external power supply voltages of 5V, 3V and 1.8V are all supported. For an operating margin, the reference voltage generating part 10 may be provided to stably operate at an external power supply voltage within a voltage range between 1.5V and 5V, and to generate a constant reference voltage. Where a stable operation of the reference voltage generating part 10 is not secured within a voltage range of the external power supply voltage VDD_EXT, it may be difficult or impossible to maintain the reference voltage constant in a lower operating voltage range and in a higher operating voltage range. Thus, the reference voltage VREF may be varied at a lower operating voltage range and/or at a higher operating voltage range, and the internal power supply voltage VDD_INT may not be maintained constant.
Accordingly, because a semiconductor integrated circuit device including the reference voltage generating part 10 may be applied to many systems, a stable operation of the reference voltage generating part 10 may need to be secured within a relatively wide voltage range.
FIG. 2 is a block diagram showing another conventional internal power supply voltage generating device.
Referring to FIG. 2, an internal power supply voltage generating device may include a reference voltage generating part 20 for generating a reference voltage VREF using an internal power supply voltage VDD_INT feedback, and an internal power supply voltage generating part 21 for generating the internal power supply voltage VDD_INT using the reference voltage VREF.
Unlike the internal power supply voltage generating device illustrated in FIG. 1, the reference voltage generating part 20 illustrated in FIG. 2 may use the internal power supply voltage VDD_INT instead of an external power supply voltage as its operating voltage, where the internal power supply voltage generating part 21 may use the external power supply voltage as its operating voltage.
The above-described problem of the device illustrated in FIG. 1 is addressed by the device illustrated in FIG. 2, but problems may arise relating to start-up of the reference voltage generating part 20 and the internal power supply voltage generating part 21.
For example, at start-up, the internal power supply voltage generating part 21 may generate the internal power supply voltage VDD_INT by generating the reference voltage VREF via the reference voltage generating part 20 and generating the internal power supply voltage VDD_INT based on the reference voltage VREF. It may be difficult or impossible to secure a normal operation of the reference voltage generating part 20 at a start-up point in time when the internal power supply voltage VDD_INT is not generated normally due to the above-described structural feedback characteristic. Accordingly, the internal power supply voltage generating part 21 may not generate the internal power supply voltage VDD_INT normally.
FIG. 3 is a timing diagram showing start-up of an internal power supply voltage generating device illustrated in FIG. 2.
As understood from FIG. 3, the internal power supply voltage VDD_INT may not be generated normally because of an abnormal start-up of the reference voltage generating part 20, though an external power supply voltage VDD_EXT is applied. In other words, an internal power supply voltage generating device illustrated in FIG. 2 may have the structure where an internal power supply voltage VDD_INT is used as an operating voltage of a reference voltage generating part 20 and an internal power supply voltage generating part 21 generates the internal power supply voltage VDD_INT using a reference voltage VREF. Accordingly, it may be difficult to generate a reference voltage VREF having a given level via the reference voltage generating part 20 illustrated in FIG. 2. Therefore, the internal power supply voltage VDD_INT may not have a required level.